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mf425 - 05 technical manual s1d16000 series technical manual ieee1394 controller s1r76801f00a technical manual s1d16000 series epson electronic devices website electronic devices marketing division first issue november,1990 printed may,2001 in japan h a 4.5mm this manual was made with recycle paper, and printed using soy-based inks.
in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notics. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no repersesnation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ?seiko epson corporation 2001, all rights reserved.
the information of the product number change starting april 1, 2001 the product number will be changed as listed below. to order from april 1, 2001 please use the new product number. for further information, please contact epson sales representative. configuration of product number l devices s1 d 16006 d 00a0 00 packing specification specifications shape (d:chip, t:tcp) model number model name (d:lcd driver) product classification (s1:semiconductors) comparison table between new and previous number previous number new number sed1606d 0a s1d16006d00a * sed1606d 0b s1d16006d00b * sed1606f 0a s1d16006f00a * sed1606d 1a s1d16006d01a * sed1606d 1b s1d16006d01b * sed1640d 0b s1d16400d00b * sed1651d 0a s1d16501d00a * sed1670d 0a S1D16700d00a * sed1670d 1a S1D16700d01a * sed1670d 0b S1D16700d00b * sed1670d 1b S1D16700d01b * sed1672d 0a s1d16702d00a * sed1672d 1a s1d16702d01a * sed1672d 0b s1d16702d00b * sed1672d 1b s1d16702d01b * sed1672f 0a s1d16702f00a *
contents s1d 16000 series selection guide s1d 16006 ...................................................... 1-1 s1d 16400 ...................................................... 2-1 s1d 16501 ...................................................... 3-1 s1d 16700 ...................................................... 4-1 s1d 16702 ...................................................... 5-1
selection guide
s1d16000 (sed1600) series segment drivers s1d16006d00a * (sed1606d 0a ) s1d16006d00b * (sed1606d 0b ) s1d16006f00a * 2.7 to 5.5 8 to 28 (sed1606f 1a ) s1d16006d01a * (sed1606d 1a ) s1d16006d01b * (sed1606d 1b ) s1d16400d00b * 2.7 to 5.5 8 to 28 (sed1640d 0b ) 4-bit parallel part number supply voltage range (v) lcd voltage range (v) duty outputs data bus 80 1/100 to 1/300 common drivers package 1/100 to 1/300 80 4-bit parallel s1d16501d00a * 2.7 to 5.5 8 to 28 (sed1651d 0a ) S1D16700d00a * (sed1670d 0a ) S1D16700d01a * (sed1670d 1a ) 2.7 to 5.5 8 to 28 S1D16700d00b * (sed1670d 0b ) S1D16700d01b * (sed1670d 1b ) s1d16702d00a * (sed1672d 0a ) s1d16702d01a * (sed1672d 1a ) s1d16702d00b * 2.7 to 5.5 8 to 28 (sed1672d 0b ) s1d16702d01b * (sed1672d 1b ) s1d16702f00a * (sed1672f 0a ) al pad chip (zigzag positioning) al pad chip (inh type) al pad chip (doff type) au bump chip (inh type) au bump chip (doff type) al pad chip (inh type) al pad chip (doff type) au bump chip (inh type) au bump chip (doff type) qfp5-80pin (inh type) part number supply voltage range (v) lcd voltage range (v) duty outputs package 1/64 to 1/300 68 1/64 to 1/300 1/64 to 1/300 100 100 al pad chip (for cob) au bump chip qfp5-100pin al pad chip (doff type) au bump chip (doff type) au bump chip (slim chip)
s1d16006 series rev.2.1
C i C contents 1. description .................................................................................................................. .............................1-1 2. features ..................................................................................................................... ............................... 1-1 3. block diagram ................................................................................................................ ......................... 1-2 4. pin description .............................................................................................................. .......................... 1-3 5. pad .......................................................................................................................... ......................................1-4 6. pin layout ................................................................................................................... ............................... 1-6 7. functional description ....................................................................................................... ................ 1-7 8. timing chart ................................................................................................................. ............................1-8 9. absolute maximum ratings ..................................................................................................... ............ 1-9 10. electrical characteristics .................................................................................................. .......... 1-10 11. lcd drive power ............................................................................................................. ....................... 1-13 12. typical circuit diagram ..................................................................................................... ................ 1-14 rev. 2.1
s1d16006 series rev.2.1 epson 1C1 1. description the s1d16006 series is an 80 output segment (column) driver which is suitable for driving a very high capacity dot-matrix lcd panels. it is intended to be used in conjunction with the S1D16700/16702 as a pair. the s1d16006 series is featured in a high quality of picture in lcd display. it employs a high-speed enable chain system which is favorable to a low-power driving. allowed to be operated with a low voltage in the logic system power supply, it can meet a wide range of applications. 2. features ? number of lcd drive output segments: 80 ? low current consumption ? low voltage operation: C2.7 v (max.) ? wide range of lcd drive voltages: C8 v to C28 v ? high-speed and low-power data transfer enabled by means of a 4-bit bus and chain enable support shift clock frequency: 6.5 mhz (at C2.7 v) 10.0 mhz (at C4.5 v) ? selectable pin output shift direction (s1d16006d01a * ) ? adjustable offset bias of lcd power to a v dd level ? logic system power supply : C2.7 v to C5.5 v ? non-bias display off function ? chip packaging s1d16006d00a * (al-pad die form) s1d16006d00b * (au bump die form) s1d16006d01a * (al-pad die form) s1d16006d01b * (au bump die form) pkg s1d16006f00a * (qfp5-100 pin) ? no radial rays countermeasure taken in designing
s1d16006 series 1C2 epson rev.2.1 o 0 o79 v0 v2 v5 v3 fr lp v v d3 to d0 shl eio1 eio2 xscl lcd driver 80 bit level shifter 80 bit enable shift register latch 80 bit data register 80 bit dspoff ss dd *1 dummy terminal nc when s1d16006d00 ** is used. dspoff terminal when s1d16006d01 ** is used *1 3. block diagram
s1d16006 series rev.2.1 epson 1C3 function segment (column) output for lcd driving the output changes at the lp falling edge. display data input display data shift clock input (falling edge trigger) display data latch pulse input (falling edge trigger) enable input/output to be set to input or output according to the shl input level. the output is reset by the lp input. upon the end of fetching of 80-bit data, the system starts up automatically to high. shift direction selection and eio pin i/o control input when data is input to (d3, d2 ... d0 ) pins sequentially in order of (a3, a2, a1, a0), (b3, b2, b1, b0) ... (t3, t2, t1, t0), the relationship between the data and segment output becomes as shown in the table below: (note) the relationship between the data and segment output is determined irrespective of the number of shift clock inputs. lcd drive output ac converted signal input force input of blank v0 level is forcibly set by entering low level (available with s1d16006d01 ** alone). logic power supply v dd : 0 v v ss : C2.7 v to C5.5 v lcd drive circuit power supply v dd : 0 v v 5 : C8 v to C28 v v dd 3 v 0 3 v 2 3 6/9 v 5 3/9 v 5 3 v 3 3 v 5 when used at a same potential, v 0 and v dd are used by grounding them close to the ic chip. number of pins pin name o0 ~ o79 d0 ~ d3 xscl lp eio1, eio2 shl fr dspoff v dd , v ss v0, v2, v3, v5 *1 80 4 1 1 2 1 1 1 2 4 o output eio shl 79 78 77 2 1 0 eio1 eio2 low a3 b2 c1 . . . t2 t1 t0 output input high t0 t1 t2 . . . a1 a2 a3 input output i/o o i i i i/o i i i power supply power supply *1 be sure to connect v 0 to v 5 to their lcd power, respectively. total: 100 s1d16006d00 ** (including four nc4) s1d16006d01 ** (including four nc3) 4. pin description
s1d16006 series 1C4 epson rev.2.1 5. pad pad layout chip size: ........................... 5.59 mm 3.50 mm pad pitch: ........................... 0.153 mm (min.) chip thickness: ................... 0.400 mm (al-pad die form) 0.525 mm (au-bump die form) au bump specifications [reference values] bump size: 117 m m 109 m m 20 um bump height: 17 m m to 28 m m (details shall be stipulated in the delivery specification.) al-pad die form pad opening 87 76 m m (0.0) y x 75 50 65 80 60 70 55 85 90 95 100 1 5 10 15 20 25 30 35 40 45 d1606d 0b
s1d16006 series rev.2.1 epson 1C5 pad actual dimensions no. name x y 1 o0 C2227 C1578 2 o1 C2073 3 o2 C1920 4 o3 C1766 5 o4 C1612 6 o5 C1459 7 o6 C1305 8 o7 C1152 9 o8 C998 10 o9 C845 11 o10 C691 12 o10 C537 13 o12 C384 14 o13 C230 15 o14 C76 16 o15 77 17 o16 231 18 o17 384 19 o18 538 20 o19 692 21 o20 845 22 o21 999 23 o22 1152 24 o23 1306 25 o24 1460 26 o25 1613 27 o26 1767 28 o27 1921 29 o28 2074 30 o29 2228 31 o30 2381 32 o31 2622 C1346 33 o32 C1188 34 o33 C1029 unit ( m m) pad actual dimensions no. name x y 69 o68 C537 1578 70 o69 C691 71 o70 C846 72 o71 C998 73 o72 C1152 74 o73 C1305 75 o74 C1459 76 o75 C1613 77 o76 C1766 78 o77 C1920 79 o78 C2073 80 o79 C2227 81 eio2 C2381 82 d0 C2622 1346 83 d1 1192 84 d2 1039 85 d3 885 86 dummy 732 87 dummy 578 88 dummy 424 89 *1 271 90 v dd 106 91 v ss C58 92 v0 C224 93 v2 C389 94 v3 C553 95 v5 C718 96 shl C2611 C885 97 xscl C1039 98 lp C1192 99 fr C1346 100 eio1 C2381 C1578 pad actual dimensions no. name x y 35 o34 2622 C871 36 o35 C713 37 o36 C554 38 o37 C396 39 o38 C238 40 o39 C79 41 o40 79 42 o41 238 43 o42 396 44 o43 554 45 o44 713 46 o45 871 47 o46 1029 48 o47 1188 49 o48 1346 50 o49 2381 1578 51 o50 2228 52 o51 2074 53 o52 1921 54 o53 1767 55 o51 1613 56 o55 1460 57 o56 1306 58 o57 1152 59 o58 999 60 o59 845 61 o60 692 62 o61 538 63 o62 384 64 o63 231 65 o64 77 66 o65 C76 67 o66 C230 68 o67 C384 *1: pad no.89 is dummy when s1d16006d00 ** is used. it will be dspoff with s1d16006d01 ** . pad center coordinate
s1d16006 series 1C6 epson rev.2.1 1o0 2o1 3o2 4o3 5o4 6o5 7o6 8o7 9o8 10 o9 11 o10 12 o11 13 o12 14 o13 15 o14 16 o15 17 o16 18 o17 19 o18 20 o19 21 o20 22 o21 23 o22 24 o23 25 o24 26 o25 27 o26 28 o27 29 o28 30 o29 31 o30 32 o31 33 o32 34 o33 35 o34 36 o35 37 o36 38 o37 39 o38 40 o39 41 o40 42 o41 43 o42 44 o43 45 o44 46 o45 47 o46 48 o47 49 o48 50 o49 51 o50 52 o51 53 o52 54 o53 55 o54 56 o55 57 o56 58 o57 59 o58 60 o59 61 o60 62 o61 63 o62 64 o63 65 o64 66 o65 67 o66 68 o67 69 o68 70 o69 71 o70 72 o71 73 o72 74 o73 75 o74 76 o75 77 o76 78 o77 79 o78 80 o79 81 eio2 82 d0 83 d1 84 d2 85 d3 86 nc 87 nc 88 nc 89 *1 90 v dd 91 v ss 92 v0 93 v2 94 v3 95 v5 96 shl 97 xscl 98 lp 99 fr 100 eio1 pin no. name pin no. name pin no. name pin no. name pin no. name s1d16006f index package type: qfp? 100pin 50 81 1 30 80 51 *1: pad no.89 is dummy when s1d16006d00 ** is used. it will be dspoff with s1d16006d01 ** . 6. pin layout
s1d16006 series rev.2.1 epson 1C7 7. functional description enable shift register this is a bidirectional shift register with which the shift direction is selected by shl input. the output of this shift register is used to store the data bus signals to data register. when the enable signal is in the disable status, the internal clock signal and data bus are fixed to low and the system is made into the power save mode. when using two or more segment drivers, connect the eio pin of each driver in a cascade arrangement and the eio pin of the leading driver to v dd . since the enable controller circuit automatically detects that the data for 80 bits have been fetched thoroughly and then transfers the enable signal to the controller, it is not necessary to provide the control signal using the control lsi. data register this is a register used to convert the data bus signal into serial or parallel signal through the enable shift register output. consequently, the relationship between the serial display data and segment output is determined irrespective of the number of shift clock inputs. latch this latch is used to fetch the content of data register at the lp falling edge trigger and to send its output to the level shifter. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver this driver outputs the lcd drive voltage. the relationship among the data bus signal, ac converted signal fr and segment output voltage is as shown in the table below: data bus fr o output voltage signal high v 0 high low v 5 high v 2 low low v 3 (s1d16006d00 ** ) (s1d16006d01 ** ) dspoff data bus fr o output voltage signal high high high v 0 low v 5 high low high v 2 low v 3 low v 0
s1d16006 series 1C8 epson rev.2.1 1 to 3 stand for a cascaade no. of driver. eio 3 lp lp lp latch data latch data fr dspoff xscl d0 to d3 eio 1 eio 2 fr v 0 v 2 v 3 v 5 h hh ll l l hh ll hh hh ll l 20 1 2 3 123 20 123 123 20 20 200 200 199 1 2 1 200 199 1 2 34 when the duty is 1/200 (reference example) s1d16006d00 ** s1d16006d01 ** when s1d16006d01 ** is used: the driver output is forcibly switched to v0 output upon switching of dspoff 8. timing chart
s1d16006 series rev.2.1 epson 1C9 9. absolute maximum ratings notes: 1. all the above voltage is based on v dd = 0v. 2. the storage temperature 1 stipulates the temperature by unit of a chip. 3. the voltage of v 0 , v 2 and v 3 must always satisfy the condition of v dd 3 v 0 3 v 2 3 v 3 3 v 5 . 4. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off. parameter symbol rating unit power voltage (1) v ss C7.0 to +0.3 v power voltage (2) v 5 C30.0 to +0.3 v power voltage (3) v 0 , v 2 , v 3 v 5 C0.3 to v dd +0.3 v input voltage v i v ss C0.3 to v dd +0.3 v output voltage v o v ss C0.3 to v dd +0.3 v eio output current i o 20 ma operating temperature topr C40 to + 85 c storing temperature 1 tstg 1 C65 to +150 c v dd =0v system side v v v v v v v v cc dd ss 5 3 2 gnd 5v dd ?v ?8v 0
s1d16006 series 1C10 epson rev.2.1 symbol v ss v 5 v 5 v 0 v 2 v 3 v ih v il v oh v ol i li i li/o i ss r seg i ss i 5 c i c i/o condition C v ss =C2.7 to C5.5v function recommended value recommended value recommended value v ss =C2.7 to C5.5v v ss =C2.7 to C5.5v i oh =C0.6ma i ol =0.6ma v ss v in v dd v ss v in v dd v5=C28.0 to C14.0v v ih =v dd , v il =v ss d v on =0.5v v 5 =C20.0v v 3 =13/15v 5 v 2 =2/15v 5 v 0 =v dd ta=25 c v ss =C5.0v, v ih =v dd v il =v ss , f xscl =2.69mhz f lp =16.8khz, f fr =70hz input data: dice display at no load v ss =C3.0v other conditions are the same as v ss = -5 v v ss =C5.0v, v 0 =0.0v, v 2 =C9.3v v 3 =C18.6v, v 5 =C28.0v other conditions are the same as in the item of i ss . freq.=1mhz ta=25 c by unit of a chip min. C5.5 C28.0 C v dd C2.5 3/9v 5 v 5 0.2v ss C v ddC 0.4 C C C C C C C C C C typ. C5.0 C C C C C C C C C C C C 1.2 0.10 0.07 0.05 C C max. C2.7 C12.0 C8.0 v dd C 6/9v 5 C 0.8v ss C v ss +0.4 2.0 5.0 25 1.6 0.2 0.15 0.08 8 15 unit v v v v v v v v v v m a m a m a k w ma ma pf pf applicable pin v ss v 5 v 5 v 0 v 2 v 3 eio1, eio2, fr, d0 to d3, xscl, shl, lp eio1, eio2 d0 to d3, lp, fr xscl, shl eio1, eio2 v ss o0 to o79 v ss v 5 d0 to d3, lp, fr xscl, shl eio1, eio2 parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage low input voltage high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - unless otherwise specified, v dd = v 0 = 0v, v ss = C5.0v 10% and ta = C40 to 85 c. 10. electrical characteristics dc characteristics
s1d16006 series rev.2.1 epson 1C11 v ss =C5.0v 0.5v, ta=C40 to 85 c parameter symbol condition min. max. unit xscl period t c C 100 C ns xscl high pulsewidth t wch C30Cns xscl low pulsewidth t wcl C30Cns data setup time t ds C20Cns data hold time t dh C10Cns xscl-rise to lp-rise time t ld C0Cns lp-fall to xscl-fall time t lh C40Cns lp high pulsewidth t wlh *3 40 C ns allowable fr delay time t df C C900 +900 ns eio setup time t sue C35Cns v ss =C4.5v to C2.7v, ta=C40 to 85 c parameter symbol condition min. max. unit v ss =C2.7v *1 153 C xscl period t c ns v ss =C3.0v *2 133 C xscl high pulsewidth t wch C50Cns xscl low pulsewidth t wcl C50Cns data setup time t ds C30Cns data hold time t dh C15Cns xscl-rise to lp-rise time t ld C0Cns v ss =C2.7v 75 C lp-fall to xscl-fall time t lh ns v ss =C3.0v 65 C v ss =C2.7v *3 75 C lp high pulsewidth t wlh ns v ss =C3.0v *3 65 C allowable fr delay time t df C C900 +900 ns v ss =C2.7v 60 C eio setup time t sue ns v ss =C3.0v 51 C *1 equivalent to 6.5 mhz *2 equivalent to 7.5 mhz *3 t wlh stipulates the time when lp is high and xscl is low. *4 t r and t f of input signal are stipulated by unit of 20 ns. *5 at a high-speed operation, t r and t f = {t c C (t dcl + t sue )}/2 t wlh t df t lh t wch t wcl t c t sue t dh t ds t ld fr lp xscl d3 to d0 ei01,2 (in) v ih =0.2 v ss v il =0.8 v ss ac characteristics input timing characteristics
s1d16006 series 1C12 epson rev.2.1 fr lp t er t lsd t frsd t dcl xscl eio1, 2 (out) v on =0.2 v ss v ol =0.8 v ss o n (seg) vn?.5 vn+0.5 v ih =0.2 v ss v il =0.8 v ss v dd =C5.0 0.5v, v 5 =C12.0 to C28.0v parament symbol condition min. max. unit eio reset time t er C90ns cl=15pf (eio) eio output delay time t dcl C55ns lp to seg output delay time t lsd C 200 ns cl=100pf (on) fr to seg output delay time t frsd C 400 ns v dd =C4.5v to 2.7v, v 5 =C12.0 to C28.0v parament symbol condition min. max. unit eio reset time t er C 150 ns cl=15pf v ss =C2.7v C 88 ns eio output delay time t dcl (eio) v ss =C3.0v C 77 ns lp to seg output delay time t lsd C 400 ns cl=100pf (on) fr to seg output delay time t frsd C 800 ns *1 t r and t f of input signal are stipulated by unit of 20 ns. *2 at a high-speed operation, t r and t f = {t c C (t dcl + t sue )}/2 output timing characteristics
s1d16006 series rev.2.1 epson 1C13 11. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is optimum to divide the resistance of potential between v 5 and v dd to drive the lcd using the voltage follower with an operational amplifier. in taking into consideration of such a case using the operational amplifier, the maximum potential level v 0 for lcd driving has been made a separate pin from v dd . when the potential of v 0 lowers than that of v dd and the potential difference between the two becomes larger, however, the capacity of lcd drive output driver lowers. to avoid it, use the system with the potential difference of 0 v to 2.5 v between v0 and v dd . when no operational amplifier is used, connect v 0 and v dd close to the ic chip. when a series resistance exists in the power supply line of v 5 and v dd , a voltage drop of v 5 and v dd occurs at the lsi power supply pin, the relationship with the lcds intermediate potential (v dd 3 v0 3 v2 3 v3 3 v 5 ) cannot be met, this causing the lsi to be broken down in some cases. when a protection resistor is inserted, it is necessary to stabilize the voltage by capacitance. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating or above v ss = C2.6 v, and when the lcd driving signal is output before the applied voltage to the lcd driving system is stabilized, an overcurrent flows and lsi breaks down in some cases. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off .. lcd driving system off ? logic system off or simultaneous off of the both for a countermeasure to such overcurrent, it is effective to put a high-speed melting fuse or protection resistor in series with the lcd power unit. it is then required to select the optimum value in the protection resistance according to the capacitance of lc cell. until the lcd driver voltage stabilizes. it is recommended to set the lcd driver output potential to v 0 using the display off function (dspoff). power on power off t1.t2.t3 0 sec t2 > = t1 v v dd power on/off sequence when s1d16006d01 ** is used v dd v ss v ss dspoff v 5 t3 t3
s1d16006 series 1C14 epson rev.2.1 80 yd yscl shl pr doff (v dd ) lp xscl shl dl0 to 3 di01 di02 di01 di02 S1D16700 S1D16700 80 80 s1d16006 s1d16006 s1d16006 ei01 v dd ei02 ei01 ei02 ei01 (8) (2) (1) ei02 640 200 dot 1/200 duty r r + r r r + + + + v 0 v 1 v 2 v 3 v 4 v 5 v 5 v ss v dd 100 100 12. typical circuit diagram configuration drawing of large screen lcd
s1d16400
C i C contents 1. description .................................................................................................................. .............................2-1 2. features ..................................................................................................................... ............................... 2-1 3. block diagram ................................................................................................................ ......................... 2-2 4. functions of the terminals ................................................................................................... ............ 2-3 5. pad layout ................................................................................................................... .............................. 2-4 6. pad center coordinates ....................................................................................................... ..............2-5 7. function descriptions ........................................................................................................ ................. 2-6 8. absolute maximum rating ...................................................................................................... .............2-7 9. electrical characteristics ................................................................................................... ........... 2-8 10. regarding the lcd driving power ............................................................................................. .... 2-12 11. an example of connection .................................................................................................... ........... 2-13
s1d16400 series epson 2C1 1. description the s1d16400 is an 80 output segment (column) driver for use in combination with an S1D16700/16702. it is provided with high-vision measure of the lcd display and adopts high speed inable chain system for low power operation and slim chip shape suitable for minimizing of the lcd panel. also, low voltage operation of the logic power source suits a wide range of applications. 2. features ? lcd driver output number : 80 ? ultra-slim chip ? low current consumption ? low voltage operation : C2.7v max. ? wide range of liquid crystal drive voltage : C8 to C28v ? high speed and low power data transfer is possible by adoption of the 4 bit bus inable chain system. shift clock frequency 6.5mhz (at C2.7v) 7.5mhz (at C3.0v) ? non-bias display off function ? pin selection of the output shift direction is available. ? offset bias regulation of the liquid crystal power is possible depending on the v dd level. ? logic system power source : C2.7v to C5.5v ? product shapes chip : s1d16400d00b * (au bump article)
s1d16400 series 2C2 epson o 0 o79 v0 v2 v5 v3 fr lp dspoff v v d0 to d3 shl eio1 eio2 xscl lcd driver 80 bit level shifter 80 bit inable shift register latch 80 bit data register 80 bit ss dd 3. block diagram
s1d16400 series epson 2C3 terminal numbers of i/o functions names terminals o0 ~ o79 o lcd driving segment (column) output. 80 the output level varies by the trailing edge of the lp. d0 ~ d3 i display data input 4 xscl i shift clock input of display data (trailing edge trigger) 1 lp i latch pulse input of display data (trailing edge trigger) 1 eio1, eio2 i/o inable input and output. 2 set to input or output depending on the shl input level. the output is reset by the lp input and, after receiving 80 bit data, it automatically rises to high. shl i shifting direction choice and input/output controlling input to the 1 eio terminal. when data are input to (d3, d2 ...d0) terminals in the order of (a,b,c,d,e,f,g,h).....(w,x,y,z), relations between data and segment outputs are as follows: (note) relations between data and segment outputs are determined independent from the shift clock number. fr i input of the alternating signal of the lcd drive output. 1 v dd , v ss power power supply for the logics v dd :0v 3 source v ss : C2.7 ~ C5.5v v0, v2, power power supply for the lcd driver circuit 8 v3, v5 source v dd :0v v 5 : C8 ~ C28v v dd > > = v 0 > > = v 2 > > = 6/9 v 5 *1 3/9 v 5 > > = v 3 > > = v 5 dspoff i forced blank input 1 at the low level, it forces the output to v0 level. * when using this function, the unit may be used in common with S1D16700 * 01 ** . *1 be sure to connect pairs of v0 - v5 to respective lcd power sources. total 107 (including nc5) o output eio shl 79 78 77 2 1 0 eio1 eio2 low a b c . . . x y z output input high z y x . . . c b a input output 4. functions of the terminals
s1d16400 series 2C4 epson 5. pad layout 100 105 95 90 85 80 75 70 65 60 55 50 45 40 25 20 15 10 5 1 35 30 (0,0) chip size ............................ 11.59mm x 1.40mm pad pitch ............................ 105 m m (min.) chip thickness .................... 625 m m 25 m m au bump specification (s1d16400d00b * ) reference values bump size a 160 m m 80 m m 4 m m (pad no. 2 ~ 26) bump size b 86 m m 91 m m 4 m m (pad no. 1, 27, 37 and 98) bump size c 86 m m 68 m m 4 m m (pad no. 28 ~ 36 and 99 ~ 107) bump size d 82 m m 74 m m 4 m m (pad no. 38 ~ 97) bump height a ~ d 22.5 5.5 m m (pad no. 1 ~ 107)
s1d16400 series epson 2C5 x-axis of y-axis of pad no. pad name coordinates coordinates 74 o46 C1161 553 75 o47 C1340 76 o48 C1518 77 o49 C1697 78 o50 C1875 79 o51 C2054 80 o52 C2233 81 o53 C2411 82 o54 C2590 83 o55 C2768 84 o56 C2947 85 o57 C3126 86 o58 C3304 87 o59 C3483 88 o60 C3661 89 o61 C3840 90 o62 C4019 91 o63 C4197 92 o64 C4376 93 o65 C4554 94 o66 C4733 95 o67 C4912 96 o68 C5090 97 o69 C5269 98 o70 C5644 546 99 o71 418 100 o72 313 101 o73 207 102 o74 102 103 o75 C4 104 o76 C109 105 o77 C215 106 o78 C320 107 o79 C426 1 eio2 C544 x-axis of y-axis of pad no. pad name coordinates coordinates 38 o10 5269 553 39 o11 5090 40 o12 4912 41 o13 4733 42 o14 4554 43 o15 4376 44 o16 4197 45 o17 4019 46 o18 3840 47 o19 3661 48 o20 3483 49 o21 3304 50 o22 3126 51 o23 2947 52 o24 2768 53 o25 2590 54 o26 2411 55 o27 2233 56 o28 2054 57 o29 1875 58 o30 1697 59 o31 1518 60 o32 1340 61 o33 1161 62 o34 982 63 o35 804 64 o36 625 65 o37 447 66 o38 268 67 o39 89 68 o40 C89 69 o41 C268 70 o42 C447 71 o43 C625 72 o44 C804 73 o45 C982 x-axis of y-axis of pad no. pad name coordinates coordinates 2 v0 C5345 C541 3 v2 C5164 4 v3 C4984 5 v5 C4594 6v ss C4091 7 dummy C3839 8 shl C3587 9 dummy C3065 10 dummy C2828 11 v dd C2590 12 dspoff C2086 13 fr C1583 14 lp C1079 15 xscl 1079 16 d0 1583 17 d1 2086 18 d2 2590 19 dummy 3065 20 d3 3587 21 dummy 3839 22 v ss 4091 23 v5 4594 24 v3 4984 25 v2 5164 26 v0 5345 27 eio1 5644 C544 28 o0 C426 29 o1 C320 30 o2 C215 31 o3 C109 32 o4 C4 33 o5 102 34 o6 207 35 o7 313 36 o8 418 37 o9 546 6. pad center coordinates
s1d16400 series 2C6 epson data bus dspoff fr o output voltage signals high v 0 high low v 5 high high v 2 low low v 3 low v 0 7. function descriptions inable shift registor the inable shift registor is a bidirectional shift registor wherewith the shift direction is determined by the shl inputs and outputs of such shift registor are used to store data bus signals to the data registor. when inable signals are in the disable state, the internal clock signal and data bus are fixed to low to become the power save mode. when using multiple units of the segment driver, eio terminals of each driver should be connected by the cascade connection and the eio terminals of the top end driver should be connected to v dd . (refer to the example of the connection) since the inable control circuit automatically detects when all the 80 bit data are taken in and automatically transfers the inable signal, control signals from a controlling lsi are not needed. data registor this is a registor for serial and parallel conversion of data bus signals by means of the inable shift registor output. consequently, the relations between the serial display data and segment outputs are determined independent from the shift clock input number. latch it takes in the contents of the data registor by means of the trailing edge trigger of the lp to transmit the output to the level shifter. level shifter this is a level interface circuit to convert the voltage level of signals from logic level to lcd driving level. lcd driver it outputs the lcd drive voltage. relations among data bus signals, alternating signals fr and the segment output voltage are given below.
s1d16400 series epson 2C7 items symbols ratings unit power voltage (1) v ss C7.0 ~ +0.3 v power voltage (2) v 5 C30.0 ~ +0.3 v power voltage (3) v 0 , v 2 , v 3 v 5 C0.3 ~ v dd +0.3 v input voltage v i v ss C0.3 ~ v dd +0.3 v output voltage v o v ss C0.3 ~ v dd +0.3 v eio output current i 01 20 ma working temperature topr C40 ~ +85 c storing temperature 1 tstg 1 C65 ~ +150 c storing temperature 2 tstg 2 C55 ~ +100 c v dd v 2 v 3 v 5 v ss ?v ?8v v 0 8. absolute maximum rating note 1) all the above voltage is based on v dd = 0v. note 2) the storing temperature 1 specifies that of chips proper and the storing temperature 2 specifies that of tab packages. note 3) voltage of v 0 , v 2 and v 3 should always be maintained under a condition of v dd > = v 0 > = v 2 > = v 3 > = v 5 . note 4) when logic power becomes floating state or if v ss = C2.6 or beyond while the lcd driver power source is being applied, the lsi may be permanently damaged and avoid such circumstances. pay extra attention to the power sequence at times of turning on and turning off the power supply.
s1d16400 series 2C8 epson unless otherwise designated, v dd = v0 = 0v, v ss = C5.0v 10% and ta = C40 to 85 c. items symbols conditions applicable terminals min. typ. max. unit power voltage (1) v ss v ss C5.5 C5.0 C2.7 v recommended v 5 v ss =C2.7 ~ C5.5v v 5 C28.0 C12.0 v operating voltage operatable voltage v 5 function v 5 -8.0 v power voltage (2) v 0 recommended value v 0 v dd C2.5 v dd v power voltage (3) v 2 recommended value v 2 3/9v 5 v power voltage (4) v 3 recommended value v 3 v 5 6/9v 5 v high level input voltage v ih v ss =C2.7 ~ C5.5v eio1, eio2, fr, 0.2v ss v d0 ~ d3, xscl, low level input voltage v il shl, lp, dspoff 0.8v ss v high level output v oh v ss =C2.7 ~ C5.5v i oh =C0.6ma eio1, eio2 v dd C0.4 v low level output v ol i ol =0.6ma v ss +0.4 v voltage input leak current i li v ss < = v in < = v dd d0 ~ d3, lp, fr 2.0 m a xscl, shl, dspoff input and output i li/o v ss < = v in < = v dd eio1, eio2 5.0 m a leak current rest current i ss v5=C28.0 ~ C14.0v v ss 25 m a v ih =v dd , v il =v ss output resistance r seg d v on =0.5v o 0 ~ o 79 1.5 2.5 k w v 5 =C20.0v v 3 =13/15?v5 v 2 =2/15?v5 v 0 =v dd average operating i ss v ss =C5.0v, v ih =v dd v ss 0.10 0.2 ma current v il =v ss , f xscl =2.69mhz consumption (1) f lp =16.8khz, f fr =70hz input data: diced display no-load v ss =C3.0v 0.07 0.15 other conditions are the same as with v ss =C5v average operating i 5 v ss =C5.0v, v 0 =0.0v, v5 0.02 0.05 ma current v 2 =C9.3v, v 3 =C18.6v, consumption (2) v 5 =C28.0v other conditions are the same as with the item i ss . input terminal c i freq.=1mhz d0 ~ d3, lp, fr, 8 pf capacity ta=25 c xscl, shl, chips proper dspoff input and output c i/o eio1, eio2 15 pf terminal capacity - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9. electrical characteristics dc characteristics
s1d16400 series epson 2C9 lp latch data fr dspoff h hh ll l l hh ll h h hh ll l v0 v2 v3 v5 200 lp 1 2 3 4 199 200 1 2 3 199 200 1 latch data fr lp xscl 20 1 2 3 20 1 2 3 20 1 3 2 1 20 d0 to d3 eio 1 eio 2 eio n * 1 2 timing diagram in case of 1/200 duty (an example) 1 ~ n indicate the cascade numbers of drivers. * in case of high speed data transfer, it is necessary to secure a longer xscl cycle in the timing of the lp pulse insertion in order to maintain the specified value of lp ? xscl ( t lh ).
s1d16400 series 2C10 epson v ss =C4.5v ~ 2.7v, ta=C40 ~ 85 c items symbols conditions min. max. unit v ss =C2.7v 153 xscl cycle t c ns v ss =C3.0v 133 xscl high level pulse duration t wch 50 ns xscl low level pulse duration t wcl 50 ns data setup time t ds 50 ns data hold time t dh 30 ns xscl ? lp rise time t ld 0ns v ss =C2.7v 75 lp ? xscl fall time t lh ns v ss =C3.0v 65 v ss =C2.7v 75 lp high level pulse duration t wlh ns v ss =C3.0v 65 fr delay permissible time t df C900 +900 ns v ss =C2.7v 50 eio setup time t sue ns v ss =C3.0v 40 *1 6.5mhz equivalence *2 7.5mhz equivalence *3 t wlh specifies the time when lp is high and, at the same time, xscl is low. *1 *2 *3 *3 v ss =C5.0v 0.5v, ta=C40 ~ 85 c items symbols conditions min. max. unit xscl cycle t c 100 ns xscl high level pulse duration t wch 30 ns xscl low level pulse duration t wcl 30 ns data setup time t ds 30 ns data hold time t dh 20 ns xscl ? lp rise time t ld 0ns lp ? xscl fall time t lh 40 ns lp high level pulse duration t wlh *3 40 ns fr delay permissible time t df C900 +900 ns eio setup time t sue 35 ns t wlh t df t lh t wch t wcl t c t sue t dh t ds t ld fr lp xscl d0 to d3 ei01,2 (in) ac characteristics input timing characteristics
s1d16400 series epson 2C11 v dd =C5.0 0.5v, v5=C12.0 ~ C28.0v items symbols conditions min. max. unit eio reset time t er 90 ns cl=15pf (eio) eio output delay time t dcl 55 ns lp ? seg output delay time t lsd 200 ns cl=100pf (0n) fr ? seg output delay time t frsd 400 ns v dd =C4.5v ~ 2.7v, v5=C12.0 ~ C28.0v items symbols conditions min. max. unit eio reset time t er 150 ns cl=15pf v ss =C2.7v 95 ns eio output delay time t dcl (eio) v ss =C3.0v 85 ns lp ? seg output delay time t lsd 400 ns cl=100pf (0n) fr ? seg output delay time t frsd 800 ns t dcl fr lp xscl eio1, 2 (out) seg t er t lsd t frsd output timing characteristics
s1d16400 series 2C12 epson 10. regarding the lcd driving power methods to obtain necessary voltage levels in order to obtain necessary voltage levels for driving of the lcd, it should be the best to divide the potential between v 5 v dd resistively to drive by means of the voltage follower by the operation amplifier. in consideration of the case of using the operation amplifier, the maximum potential level v 0 and v dd should be separated to independent terminals. nevertheless, if v 0 potential drops below the v dd potential increasing the potential difference, the capacity of the lcd driver decreases and, therefore, it is suggested that the potential difference between v0 ~ v dd be maintained within 0v ~ 2.5v. when the operation amplifier is not used, v 0 and v dd should be connected. as shown in the example of the connection, when using the resistive divider, set the resistance as low as the power capacity of the system allows. when a series resistance exist in the power line of v 5 (v dd ), voltage drop of v 5 (v dd ) at the lsi current end occurs by i5 at times of signal changes and it becomes unable to maintain the relations of the lcd with intermediate potentials (v dd > = v 0 > = v 2 > = v 3 > = v 5 ) leading to breakage of the lsi. when installing protective resistors, it is necessary to stabilize the voltage by their capacity. cautions when turning the power on and off since the lcd drive system voltage with this lsi is comparatively high, when high voltage is applied to the lcd drive system leaving the logic power floating or leaving v ss = C2.6v or over or if lcd drive signals are output before the applied voltage to the lcd drive system is stabilized, excess current may flow to break the lsi. it therefore is suggested to bring the potential of the lcd drive output to the v 0 level until the lcd drive system voltage gets stabilized using the display-off function ( dspoff ). when turning the power on or off, follow the sequence below. when turning on the power.....logic systems on ? lcd drive system on (or turn them on simultaneously). when turning off the power.....lcd drive system off ? logic system off (or turn them off simultaneously). insert quick melting fuse in series to the lcd power source for prevention of an excess current flow. it is necessary to choose the optimum value for the protective resistance matching the capacity of the liquid crystal cells.
s1d16400 series epson 2C13 yd yscl shl v lp xscl shl ?+ ?+ ?+ ?+ v0 v1 r r r r r v ss dl0 to 3 v2 v3 v4 v5 v dd + v5 fr dd 12 8 1/200 duty 100 100 S1D16700 S1D16700 dio1 dio2 dio1 dio2 80 80 s1d16400 s1d16400 eio1 eio1 eio2 eio2 s1d16400 eio1 eio2 80 640 200 dot 11. an example of connection block diagram of a large sized lcd
s1d16501 rev.1.0
C i C contents 1. description .................................................................................................................. .............................3-1 2. features ..................................................................................................................... ............................... 3-1 3. block diagram ................................................................................................................ ......................... 3-2 4. pin description .............................................................................................................. .......................... 3-3 5. pad .......................................................................................................................... ......................................3-4 6. functional description ....................................................................................................... ................ 3-6 7. timing chart ................................................................................................................. ............................3-7 8. absolute maximum ratings ..................................................................................................... ............ 3-8 9. electrical characteristics ................................................................................................... ........... 3-9 10. lcd drive power ............................................................................................................. ....................... 3-12 11. typical circuit diagram ..................................................................................................... ................ 3-13 rev.1.0
s1d16501 series rev.1.0 epson 3C1 1. description the s1d16501 is a 100 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix lcd panels. it is intended to be used in conjunction with the s1d16408 as a pair. since the s1d16501 is so designed to drive lcds over a wide range of voltages, and also the maximum potential v 0 of its lcd driving bias voltages is isolated from v dd to allow the lcd driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of lcd panels. owing to its pad layout which can minimize its pc boards mounting space in addition to its selectable bidirectional driver output sequence and as many as 100 lcd output segments of high pressure resistance and low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel. 2. features ? number of lcd drive output segments: 100 ? super slim chip configuration ? common output on resistance: 750 w (typ.) ? display capacity ... possible to display 640 480 dots. ? selectable pin output shift direction ? no bias display off function ? adjustable offset bias of lcd power to v dd level ? wide range of lcd drive voltages: C8 v to C28 v (absolute maximum rated voltage: C30 v) ? logic system power supply: C2.7 v to C5.5 v ? chip packaging s1d16501d00a * (al-pad die form) ? no radial rays countermeasure taken in designing
s1d16501 series 3C2 epson rev.1.0 o 0 o99 v0 v1 lcd driver 100 bit level shifter 100 bit bidirectional shift register 50 2 bit v4 v5 fr di3 dio2 dio1 yscl shl dspoff sel v ss v dd 3. block diagram
s1d16501 series rev.1.0 epson 3C3 number of pins pin name o0 to o99 dio1 dio2 di3 sel yscl shl dspoff fr v dd , v ss v0, v1, v4, v5 i/o o i/o i i i i i i power supply power supply 80 2 1 1 1 1 1 1 3 8 function lcd drive common (row) output the output changes at the yscl falling edge. 50 2 bits bidirectional shift register serial data input/output to be set to input or output according to the shl input the output changes at the yscl falling edge. this is the input pin of scanning pulse in the 50 2 bits configuration. when sel = low, the di3 pin to v ss or gnd. selection input of bidirectional shift register operating mode high ... 50 2 (di3 input) low ... 100 serial data shift clock input the scanning data is shifted at the falling edge. shift direction selection and dio pin i/o control input when sel = high, the di3 input is set to o50 (shl = low) or o49 (shl = high). when sel = low, the d13 input is ignored and the dio inputs are shifted continuously. lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the v 0 level instantaneously. lcd drive output converted signal input logic power supply v dd : 0 v (gnd) v ss : C2.7 v to C5.5 v lcd drive power supply v 5 : C8 v to C28 v v dd 3 v 0 3 v 1 3 v 4 3 v 5 shl o output shift direction dio1 dio2 low 0 ? 49 50 ? 99 input output high 99 ? 50 49 ? 0 ourput input respectively total: 119 4. pin description
s1d16501 series 3C4 epson rev.1.0 109 110 119 29 20 30 19 1 y x aa cc ab b b 152?- a 170?- a 475? 152?- a 153? 130? 144? (min) (min) (min) chip edge chip edge pad a opening (x, y) 110 110 m m pad no 30 to 109 pad b opening (x, y) 110 110 m m pad no 20 to 29, 110 to 119 pad c opening (x, y) 110 110 m m pad no 1 to 19 5. pad pad layout chip size: ........................... 13.43 mm 1.76 mm chip thickness: ................... 400 m m (typ.) al pad specifications (s1d16501d00a * )
s1d16501 series rev.1.0 epson 3C5 pad actual dimensions no. name x y 1 dio2 C5985 C709 2 v0 C5510 3 v1 C5035 4 v4 C4560 5 v5 C4038 6v ss C3164 7 sel C2280 8 shl C1767 9 di3 C1064 10 yscl C181 11 v dd 770 12 dspoff 1283 13 fr 2176 14 v ss 2879 15 v5 3753 16 v4 4560 17 v1 5035 18 v0 5510 19 dio1 5985 20 o0 6560 C610 21 o1 6430 C466 22 o2 6560 C321 23 o3 6430 C177 24 o4 6560 C32 25 o5 6430 112 26 o6 6560 257 27 o7 6430 401 28 o8 6560 545 29 o9 6430 690 30 o10 6079 727 31 o11 5925 32 o12 5771 33 o13 5617 34 o14 5463 35 o15 5310 36 o16 5156 37 o17 5002 38 o18 4848 39 o19 4694 40 o20 4540 41 o21 4386 42 o22 4232 unit ( m m) pad actual dimensions no. name x y 43 o23 4078 727 44 o24 3924 45 o25 3771 46 o26 3617 47 o27 3463 48 o28 3309 49 o29 3155 50 o30 3001 51 o31 2847 52 o32 2693 53 o33 2539 54 o34 2385 55 o35 2232 56 o36 2078 57 o37 1924 58 o38 1770 59 o39 1616 60 o40 1462 61 o41 1308 62 o42 1154 63 o43 1000 64 o44 846 65 o45 693 66 o46 539 67 o47 385 68 o48 231 69 o49 77 70 o50 C77 71 o51 C231 72 o52 C385 73 o53 C539 74 o54 C693 75 o55 C846 76 o55 C1000 77 o57 C1154 78 o58 C1308 79 o59 C1462 80 o60 C1616 81 o61 C1770 82 o62 C1924 83 o63 C2078 84 o64 C2232 pad actual dimensions no. name x y 85 o65 C2385 727 86 o66 C2539 87 o67 C2693 88 o68 C2847 89 o69 C3001 90 o70 C3155 91 o71 C3309 92 o72 C3463 93 o73 C3617 94 o74 C3771 95 o78 C3924 96 o76 C4078 97 o77 C4232 98 o78 C4386 99 o79 C4540 100 o80 C4694 101 o81 C4848 102 o82 C5002 103 o83 C5156 104 o84 C5310 105 o85 C5463 106 o86 C5617 107 o87 C5771 108 o88 C5925 109 o89 C6079 110 o90 C6430 690 111 o91 C6560 545 112 o92 C6430 401 113 o93 C6560 257 114 o94 C6430 112 115 o95 C6560 C32 116 o96 C6430 C177 117 o97 C6560 C321 118 o98 C6430 C466 119 o99 C6560 C610 pad center coordinates
s1d16501 series 3C6 epson rev.1.0 content of dspoff fr o output voltage shift register high v 5 high (select level) low v 0 high high v 1 (non-select low low v 4 level) low C C v 0 C 6. functional description shift register this is a bidirectional shift register to transfer common data. being a 50 2 bits configuration, this register can select 50 2 bits or 100 bits according to the status of sel. when the 50 2 bits configuration is selected, the input of the 50-bit shift register becomes d13. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver this driver outputs the lcd drive voltage. the relationship among the display blanking signal dspoff, contents of shift register, ac converted signal fr and on output voltage is as shown in the table below:
s1d16501 series rev.1.0 epson 3C7 dio1 (di3) yscl shl=low 1/200 duty fr 1 frame shift register (200 lines) dio2 o0 o1 o2 q0 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 q1 q2 dspoff * 100 lines ( * 50 lines when d13 is input where sel = high) 7. timing chart
s1d16501 series 3C8 epson rev.1.0 parameter symbol rating unit supply voltage (1) v ss C7.0 to +0.3 v supply voltage (2) v 5 C30.0 to +0.3 v supply voltage (3) v 0 , v 1 , v 4 v 5 C0.3 to +0.3 v input voltage v i v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v output current (1) i o 20 ma output current (2) i ocom 20 ma operating temperature topr C40 to + 85 c storing temperature 1 tstg 1 C65 to +150 c v dd =0v system side v v v v v v v v cc dd ss 5 4 1 gnd 5v dd ?v ?8v 0 8. absolute maximum ratings notes* 1. the voltage of v 0 , v 1 , v 4 and v 5 must always satisfy the condition of v dd 3 v 0 3 v 1 3 v 4 3 v 5 . 2. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v or less can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off.
s1d16501 series rev.1.0 epson 3C9 symbol v ss v 5 v 5 v 0 v 1 v 4 v ih v il v oh v ol i li i li/o i dds r com i ss1 i ss2 c i c i/o condition C C functional operation C C C C C i oh =C0.3ma i ol =0.3ma v ss v in 0v v ss v in 0v v 5 =C12.0 ~ C28.0v v ih =v dd , v il =v ss d v on =0.5v v 0 =v dd , v 1 =C1.5v v 4 =C18.5v v 5 =C20.0v v ss =C5.0v, v ih =v dd v il =v ss , f yscl =12khz frame frequency=60hz input data: 1/200 ta=25 c ? v ss =C3.0v other conditions are the same as v ss = C5.0 v v ss =C5.0v, v 0 =0v, v 1 =1.5v, v 4 =18.5v, v ee =v5=C20.0v other conditions are the same as in the item of iss 1. ta=25 c min. C5.5 C28.0 C 2.5 2/9v 5 v 5 0.2v ss C v ddC 0.4 C C C C C C C C C C typ. C5.0 C C C C C C C C C C C C 0.75 7 5 7 C C max. C2.7 C12.0 C8.0 0 v dd 7/9v 5 C 0.8v ss C v ss +0.4 2.0 5.0 25 1.0 15 10 15 8 15 unit v v v v v v v v v v m a m a m a k w m a m a pf pf applicable pin v ss v 5 v 5 v 0 v 1 v 4 dio1, dio2, fr, yscl, shl, di3 dspoff, sel dio1, dio2 yscl, shl, di3 dspoff, fr, sel dio1, dio2 v dd o0~o99 v ss v 5 yscl, shl, dspoff, fr, di3, sel dio1, dio2 parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage low input voltage high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance unless otherwise specified, v dd = v 0 = 0v, v ss = C5.5vC2.7v, ta = C40 to 85 c. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9. electrical characteristics dc characteristics
s1d16501 series 3C10 epson rev.1.0 t tr t f dfr t wcll t ccl t dh t ds fr v ih =0.2 v ss v il =0.8 v ss yscl dio1 dio2 di3 t wclh v ss =C5.0v 0.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 500 C ns yscl high pulsewidth t wclh C70Cns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 100 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C300 300 ns v ss =C5.0v 0.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 1000 C ns yscl high pulsewidth t wclh C 160 C ns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 200 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns ac characteristics input timing characteristics
s1d16501 series rev.1.0 epson 3C11 v ss =C5.0 10%, ta=C40 to +85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf C 350 ns (yscl - fall to on output) delay time tpd ccl v 5 =C12.0 to (dspoff to on output) delay time tpd cdoff C28.0v C 1.0 m s (fr to on output) delay time tpd cfr cl=100pf C 1.0 m s v ss =C4.5C2.7v, ta=C40 to +85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf C 400 ns (yscl - fall to on output) delay time tpd ccl v 5 =C12.0 to (dspoff to on output) delay time tpd cdoff C28.0v C 2.0 m s (fr to on output) delay time tpd cfr cl=100pf C 2.0 m s fr on yscl v ih =0.2 v ss v il =0.8 v ss v oh =0.2 v ss v ol =0.8 v ss vn?.5 vn+0.5 dspoff dio1 dio2 t pddocl t pdcdff t pdccl t pdcfr output timing characteristics
s1d16501 series 3C12 epson rev.1.0 v dd v ss v dd v ss powern on t t t t 3 5 2 v power off t 1 t t t 1 2 3 0s > = v dspoff 10. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is optimum to divide the resistance of potential between v ddh and gnd to drive the lcd using the voltage follower with an operational amplifier. in taking into consideration of such a case using the operational amplifier, the maximum potential level v 0 for lcd driving has been made a separate pin from v dd . when no operational amplifier is used in v 0 , set v 0 = v dd . when a resistive divider is used, set it to a resistance value as low as possible in the system power capacity. when a series resistance exists in the power supply line of v dd , a voltage drop of v dd occurs at the lsi power supply pin, the relationship with the lcds intermediate potential (v dd 3 v 0 3 v 1 3 v 4 3 v 5 ) cannot be met, this causing the lsi to be broken down in some cases. when a protection resistor is inserted, it is necessary to stabilize the voltage by capacitance. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating or above v ss = C2.5 v, an overcurrent flows and lsi breaks down in some cases. to avoid this, it is recommended to suppress the potential of lcd drive output to v 0 level using the display off function (dspoff) until the lcd driving system voltage is stabilized. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off ... lcd driving system off ? logic system off or simultaneous off of the both for a countermeasure to such overcurrent, it is effective to put a high-speed melting fuse or protection resistor in series with the lcd power unit. it is then required to select the optimum value in the protection resistance according to the capacitance of lc cell.
s1d16501 series rev.1.0 epson 3C13 80 yd yscl shl pr sel (gnd) lp xscl shl dspoff dl0 to 3 di01 di02 di01 di02 di3=horl s1d16501 s1d16501 80 80 s1d16408 s1d16408 s1d16408 ei01 v dd ei02 ei01 ei02 ei01 (8) (2) (1) ei02 640 200 dot 1/200 duty r r + r r r + + + + v 0 v 1 v 2 v 3 v 4 v 5 v 5 v ss v dd 100 100 11. typical circuit diagram configuration drawing of large screen lcd
S1D16700 rev.1.1
C i C contents 1. description .................................................................................................................. .............................4-1 2. features ..................................................................................................................... ............................... 4-1 3. block diagram ................................................................................................................ ......................... 4-2 4. pin description .............................................................................................................. .......................... 4-3 5. pad .......................................................................................................................... ......................................4-4 6. functional description ....................................................................................................... ................ 4-6 7. timing chart (S1D16700d01b * ) .............................................................................................................. 4-7 8. absolute maximum ratings ..................................................................................................... ............ 4-8 9. electrical characteristics ................................................................................................... ........... 4-9 10. lcd drive power ............................................................................................................. ....................... 4-12 11. connect example ............................................................................................................. ..................... 4-13 rev.1.1
S1D16700 series rev.1.1 epson 4C1 1. description the S1D16700 is a 100 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix lcd panels upto a duty ratio of 1/300. it is intended to be used in conjunction with the s1d16400 or s1d16006 as a pair. since the S1D16700 is so designed to drive lcds over a wide range of voltages, and also the maximum potential v 0 of its lcd drive bias voltages is isolated from v dd to allow the lcd driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of lcd panels. owing to its pad layout which can minimize its pc boards mounting space in addition to its selectable bidirectional driver output sequence and as many as 100 lcd output segments of high pressure resistance and low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel. and the S1D16700 * 01 ** can display 65 x 132 panel when used as a common driver of ram buit-in driver, s1d15301. 2. features ? number of lcd drive output segments: 100 ? common output on resistance: 700 w (typ.) ? display duty ratio: 1/64 to 1/300 (reference) ? display capacity: possible to display 640 480 dots when used in combination with s1d 16400d or s1d16006d. ? selectable pin output shift direction ? no-bias display off function (S1D16700 * 01 ** ) ? instantaneous display blanking enabled by inhibit function (S1D16700 * 00 ** ) ? adjustable offset bias of lcd power to v dd level ? wide range of lcd drive voltages: C7 v to C28 v (absolute maximum rated voltage: C30 v) ? logic system power supply: C2.7 v to C5.5 v ? shipping pattern S1D16700d00a * (al pad chip) S1D16700d01a * (al pad chip) S1D16700d00b * (au bump chip) S1D16700d01b * (au bump chip) S1D16700t00a * (tcp) S1D16700t01a * (tcp) ? no radial rays countermeasure taken in designing
S1D16700 series 4C2 epson rev. 1.1 com0 com99 v1 v4 lcd driver 100 bit shift register 100 bit shift register 100 bit v0 v5 fr dio1 dio2 yscl inh in S1D16700 * 00 ** doff in S1D16700 * 01 ** shl doff inh com1 com2 v dd v ss voltage control circuit 3. block diagram
S1D16700 series rev.1.1 epson 4C3 number of pins pin name com0 to com099 dio1, dio2 yscl shl doff (inh) fr v dd , v ss v0, v1, v4, v5 i/o o i/o i i i i i power supply power supply 100 2 1 1 1 (1) 1 2 4 function lcd drive common (row) output the output changes at the ys cl falling edge. 100-bit shift register serial data input/output to be set to input or output according to the shl input the output changes at the yscl falling edge. serial data shift clock input the scanning data is shifted at the falling edge. shift direction selection and dio pin i/o control input lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the v 0 level instantaneously (S1D16700d01b * ). lcd drive display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. common output = v 4 (when fr = low) common output = v 1 (when fr = high) (S1D16700d00b * ) lcd drive output ac converted signal input logic power supply v dd : 0 v (gnd) v ss : C5.0 v lcd drive power supply v 5 : C7 v to C28 v v dd 3 v 0 3 v 1 > v 4 3 v 5 shl com output shift direction dio1 dio2 low 0 ? 99 input output high 99 ? 0 ourput input inh for S1D16700 * 00 ** doff for S1D16700 * 01 ** total: 112 4. pin description
S1D16700 series 4C4 epson rev. 1.1 y x 112 1 36 37 57 93 56 92 (0,0) chip size ............................ 5.49mm 3.03mm chip thickness .................... 525 m m (au-bump die from) 400 m m (al-pad die from) 1) au bump specification reference values bump specific : high quarity au bump bump size : 90 m m 90 m m bump height : 17 m m ~ 28 m m 2) al pad specification reference values pad opening : 100 m m 100 m m 5. pad pad layout
S1D16700 series rev.1.1 epson 4C5 pad actual dimensions no. name x y 81 com85 -803 1357 82 86 -932 83 87 -1062 84 88 -1191 85 89 -1320 89 90 -1449 87 91 -1578 88 92 -1708 89 93 -1837 90 94 -1966 91 95 -2095 92 96 -2224 1357 93 97 -2473 1334 94 98 1201 95 99 1071 96 dio2 941 97 doff 715 (97) (inh) 98 fr 585 99 yscl 455 100 shl 325 101 v dd 185 102 v ss 46 103 v0 -112 104 v1 -252 105 v4 -391 106 v5 -531 107 dio1 -671 108 com0 -810 109 1 -941 110 2 -1071 111 3 -1201 112 4 -2473 -1334 pad actual dimensions no. name x y 41 com45 2584 -711 42 46 -581 43 47 -452 44 48 -323 45 49 -194 46 50 -65 47 51 65 48 52 194 49 53 323 50 54 452 51 55 581 52 56 711 53 57 840 54 58 969 55 59 1098 56 60 2584 1231 57 61 2298 1357 58 62 2168 59 63 2039 60 64 1910 61 65 1781 62 66 1652 63 67 1522 64 68 1393 65 69 1264 66 70 1135 67 71 1006 68 72 876 69 73 747 70 74 618 71 75 489 72 76 360 73 77 230 74 78 101 75 79 -28 76 80 -157 77 81 -286 78 82 -416 79 83 -545 80 84 -674 1357 pad actual dimensions no. name x y 1 com5 -2187 -1357 2 6 -2058 3 7 -1929 4 8 -1799 5 9 -1670 6 10 -1541 7 11 -1412 8 12 -1283 9 13 -1153 10 14 -1024 11 15 -895 12 16 -766 13 17 -637 14 18 -507 15 19 -378 16 20 -249 17 21 -120 18 22 10 19 23 139 20 24 268 21 25 397 22 26 526 23 27 656 24 28 785 25 29 914 26 30 1043 27 31 1172 28 32 1302 29 33 1431 30 34 1560 31 35 1689 32 36 1818 33 37 1948 34 38 2077 35 39 2206 36 40 2335 -1357 37 41 2584 -1231 38 42 2584 -1094 39 43 2584 -969 40 44 2584 -840 pad no. 97: inh for S1D16700 * 00 ** doff for S1D16700 * 01 ** pad center coordinates
S1D16700 series 4C6 epson rev. 1.1 contents of doff fr com output voltage shift register high v 5 high (select level) low v 0 high high v 1 (non-select low low v 4 level) low fixed to low C v 0 C (S1D16700 * 01 ** ) contents of inh fr com output voltage shift register high v 5 high (select level) low v 0 high high v 1 (non-select low low v 4 level) high v 1 (non-select low fixed to low low v 4 level) (S1D16700 * 00 ** ) 6. functional description shift register this is a bidirectional shift register to transfer common data. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver circuit this driver outputs the lcd drive voltage. the relationship among the display blanking signal doff, contents of shift register, ac converted signal fr and common output voltage is as shown in the table below: the relationship among the display blanking signal inh, contents of the shift register, ac converted signal fr and com output voltage is as shown in the table below:
S1D16700 series rev.1.1 epson 4C7 dio1 yscl shl=low 1/200 duty fr 1 frame shift register (200 lines) dio2 o0 o1 o2 q0 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 q1 q2 dspoff 100 lines the v 1 or v 4 non-select level is output corresponding to the fr in S1D16700d00b * or inh=low, respectively. 7. timing chart (S1D16700d01b * )
S1D16700 series 4C8 epson rev. 1.1 parameter symbol rating unit supply voltage (1) v ss C7.0 to +0.3 v supply voltage (2) v 5 C30.0 to +0.3 v supply voltage (3) v 0 , v 1 , v 4 v 5 C0.3 to +0.3 v input voltage v i v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v output current (1) i o 20 ma output current (2) i ocom 20 ma operating temperature topr C40 to + 85 c storing temperature 1 tstg C65 to +150 c v dd =0v 8. absolute maximum ratings notes: 1. the voltage of v 0 , v 1 and v 4 must always satisfy the condition of v dd 3 v 0 3 v 1 3 v 4 3 v 5 . 2. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v or more can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off.
S1D16700 series rev.1.1 epson 4C9 unless otherwise specified, v dd = v 0 = 0v, v ss = C5.0v 10%, ta = C40 to 85 c. condition C C functional operation recommended value recommended value recommended value v ss =C2.7v to C5.5v v ss =C2.7v to C5.5v i oh =C0.3ma i oh =C0.2ma (v ss =C2.7 to C4.5v) i ol =+0.3ma i ol =+0.2ma (v ss =C2.7 to C4.5v) v ss v in 0v v ss v in 0v v 5 =C7.0 to C28.0v v ih =v dd , v il =v ss d von v 5 = =0.5v C20.0v v ss =C5.0v, v ih =vdd, v il =v ss , f yscl =12khz, frame frequency=60hz input data; h at no load every 1/200 duty other conditions are the same as v ss = C3.0 v v ss =C5.0, v,=C2.0v, v 4 =C18.0v, v 5 =C20.0v other conditions are the same as in the item of i ss1 . ta=25 c min. C5.5 C28.0 C C2.5 2/9v 5 v 5 0.2v ss v ss 0.2v ss v ss C 0.4 v ss C C C C C C C C C typ. C5.0 C C C C C C C C C C C C C C 0.70 7 5 7 C C max. C2.7 C7.0 C7.0 0 v dd 7/9v 5 0 0.8v ss 0 0.85v ss 0 v ss +0.4 2.0 5.0 25 1.40 15 10 15 8 15 unit v v v v v v v v v v v v m a m a m a k w m a m a pf pf parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage (1) low input voltage (1) high input voltage (2) low input voltage (2) high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance symbol v ss v 5 v 5 v 0 v 1 v 4 v ih v il v iht v ilt v oh v ol i li i li/o i dds r com i ss1 i ss2 c i c i/o applicable pin v ss v 5 v 5 v 0 v 1 v 4 dio1, dio2, yscl, shl, fr doff, inh dio1, dio2 yscl, shl, doff, inh, fr dio1, dio2 v dd com0~com99 v ss v 5 yscl, shl, doff, inh, fr dio1, dio2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when the v 1 , v 4 , v 0 or v 5 level is output 9. electrical characteristics dc characteristics
S1D16700 series 4C10 epson rev. 1.1 fr yscl t r t f t wclh t dfr v ih =0.2 v ss v il =0.8 v ss t ds t dh t ccl t wcll dio1 dio2 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 500 C ns yscl high pulsewidth t wclh C70Cns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 100 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 1000 C ns yscl high pulsewidth t wclh C 160 C ns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 200 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns the standard applicable to t ccl , t wclh , t wcll and t ds when v ss = C2.4 v shall be 1.3 times of that applies when v ss = C2.7v to C4.5v. ac characteristics input timing characteristics
S1D16700 series rev.1.1 epson 4C11 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 30 300 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to (doff to com output) delay time tpd cdoff C28.0v C 3.0 m s (inh to com output) delay time tpd cinh cl=100pf (fr to com output) delay time tpd cfr C 3.0 m s unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 60 600 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to (doff to com output) delay time tpd cdoff C28.0v C 3.0 m s (inh to com output) delay time tpd cinh cl=100pf (fr to com output) delay time tpd cfr C 3.0 m s fr vn?.5v vn+0.5v t pddocl t pdccl t pdcfr t pdcdoff yscl v ih =0.2 v ss v il =0.8 v ss doff inh com dio1 dio2 the standard applicable at v ss = C2.4v shall be the same as that employed when v ss = C2.7v to C4.5v. output timing characteristics
S1D16700 series 4C12 epson rev. 1.1 10. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is the most simple to divide the resistance of potential as shown in the connection example. on the other hand, to obtain a high quality display, it is necessary to raise the accuracy and constancy of each voltage level and to set the divided resistance value as low as possible in the range of system power capacity. especially when a low-power lcd driving is required, set the divided resistance to a higher value and drive the lcd with a voltage follower by means of operational amplifier instead. in taking into consideration of a case where the operational amplifier is employed, the maximum potential level v0 for lcd driving has been isolated from the v dd pin. when the potential of v 0 lowers than that of v dd and the potential difference between the two becomes larger, however, the capacity of lcd drive output driver lowers. to avoid it, use the system with the potential difference of 0 v to 2.5 v between v 0 and v dd . when no operational amplifier is used, connect v 0 and v dd pins. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating, an overcurrent flows and lsi breaks down in some cases. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off ... lcd driving system off ? logic system off or simultaneous off of the both
S1D16700 series rev.1.1 epson 4C13 11. connect example 200 x 640 dot matrix lcd panel seg 79 0 seg 79 0 seg 79 0 v dd eio2 1 eio1 shl eio2 2 eio1 shl eio2 8 eio1 shl 1 2 yscl shl dio1 dio2 yscl shl dio1 dio2 fr fr S1D16700d lp yd v ss v dd v 0 v 1 v 2 v 3 v 4 v 5 vssh wf xscl xd0~xd3 v ss 6 6 r r r r 11r 322 322 fr lp d0? xscl fr lp d0? xscl fr lp d0? xscl s1d16006d com 0 99 com 0 99 note *1 it must be provided as the protective resister against overcurrent. also, the bypass capacitor (0.01 f) for noise suppression must be provided near to v ss and v5 terminals on each lsi.
s1d16702 rev.1.0
C i C contents 1. description .................................................................................................................. .............................5-1 2. features ..................................................................................................................... ............................... 5-1 3. block diagram ................................................................................................................ ......................... 5-2 4. pin description .............................................................................................................. .......................... 5-3 5. pin layout ................................................................................................................... ............................... 5-4 6. pad .......................................................................................................................... ......................................5-5 7. functional description ....................................................................................................... ................ 5-6 8. timing chart ................................................................................................................. ............................5-7 9. absolute maximum ratings ..................................................................................................... ............ 5-8 10. electrical characteristics .................................................................................................. ............ 5-9 11. lcd drive power ............................................................................................................. ....................... 5-13 12. different points from replacement product ........................................................................ 5-14 rev.1.0
s1d16702 series rev.1.0 epson 5C1 1. description the s1d16702 is a 68 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix lcd panels up to a duty ratio of 1/300. it is intended to be used in conjunction with the s1d16006 as a pair. since the s1d16006 is so designed to drive lcds over a wide range of voltages, and also the maximum potential v 0 of its lcd drive bias voltages is isolated from v dd to allow the lcd driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of lcd panels. the s1d16702 is featured in its simple pad layout which is easy in mounting pc boards in addition to its selectable bidirectional driver output sequence. it also has 68 lcd output segments of high pressure resistance and low output impedance. it can display the 65 132 panel when used as the expansion driver of s1d15301 being built in ram (s1d16702 * 01 ** ). 2. features ? number of lcd drive output segments: 68 ? common output on resistance: 700 w (typ.) ? display duty ratio: 1/64 to 1/300 (reference) ? display capacity: possible to display 640 480 dots when used in combination with s1d16006. ? selectable pin output shift direction ? instantaneous display blanking enabled by inhibit function (s1d16702 * 00 ** ) ? non-bias display off function (s1d16702 * 01 ** ) ? adjustable offset bias of lcd power to v dd level ? wide range of lcd drive voltages: C7 v to C28 v (absolute maximum rated voltage: C30 v) ? logic system power supply: C2.7 v to C5.5 v ? shipping pattern s1d16702d00a * (al pad chip) s1d16702d01a * (al pad chip) s1d16702f00a * (80-pin qfp5) ? no radial rays countermeasure taken in designing ? non-bias display off function
s1d16702 series 5C2 epson rev.1.0 com0 com67 v1 v4 lcd driver 68 bit shift register 68 bit shift register 68 bit v0 v5 fr dio1 dio2 yscl shl inh com1 com2 v dd v ss * doff * inh in s1d16702 * 00 ** doff in s1d16702 * 01 ** 3. block diagram
s1d16702 series rev.1.0 epson 5C3 number of pins pin name com0 to com67 dio1, dio2 yscl shl doff inh fr v dd , v ss v 0 , v 1 , v 4 , v 5 i/o o i/o i i i i i power supply power supply shl com output shift direction dio1 dio2 low 0 ? 67 input output high 67 ? 0 ourput input function lcd drive common (row) output the output changes at the yscl falling edge. 100-bit shift register serial data input/output to be set to input or output according to the shl input the output changes at the yscl falling edge. serial data shift clock input the scanning data is shifted at the falling edge. display data latch pulse input (falling edge trigger) shift direction selection and dio pin i/o control input lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. (s1d16702 * 01 ** ) lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. common output = v 4 (when fr = low) common output = v 1 (when fr = high) (s1d16702 * 00 ** ) lcd drive output ac converted signal input logic power supply v dd : 0 v (gnd) v ss : C5.0 v lcd drive power supply v 5 : C7 v to C28 v v dd 3 v 0 3 v 1 >v 4 3 v 5 68 2 1 1 1 (1) 1 2 4 inh in s1d16702 * 00 ** doff in s1d16702 * 01 ** 4. pin description
s1d16702 series 5C4 epson rev.1.0 124 64 41 80 65 25 40 s1d16702f00a index 1 com 3 2 com 4 3 com 5 4 com 6 5 com 7 6 com 8 7 com 9 8 com 10 9 com 11 10 com 12 11 com 13 12 com 14 13 com 15 14 com 16 15 com 17 16 com 18 17 com 19 18 com 20 19 com 21 20 com 22 pin no. pin name 21 com 23 22 com 24 23 com 25 24 com 26 25 com 27 26 com 28 27 com 29 28 com 30 29 com 31 30 com 32 31 com 33 32 com 34 33 com 35 34 com 36 35 com 37 36 com 38 37 com 39 38 com 40 39 com 41 40 com 42 41 com 43 42 com 44 43 com 45 44 com 46 45 com 47 46 com 48 47 com 49 48 com 50 49 com 51 50 com 52 51 com 53 52 com 54 53 com 55 54 com 56 55 com 57 56 com 58 57 com 59 58 com 60 59 com 61 60 com 62 61 com 63 62 com 64 63 com 65 64 com 66 65 com 67 66 dio2 67 inh 68 fr 69 yscl 70 shl 71 v dd 72 v ss 73 v 0 74 v 1 75 v 4 76 v 5 77 dio1 78 com 0 79 com 1 80 com 2 pin no. pin name pin no. pin name pin no. pin name 5. pin layout package type: qfpC5 80pin
s1d16702 series rev.1.0 epson 5C5 pad pin xy no. name pad pin xy no. name pad pin xy no. name 61 com 56 C195 1357 62 com 57 C324 63 com 58 C453 64 com 59 C583 65 com 60 C712 66 com 61 C841 67 com 62 C970 68 com 63 C1099 69 com 64 C1229 70 com 65 C1358 71 com 66 C1487 72 dm C1616 1357 73 dm C1865 1201 74 com 67 1071 75 dio2 941 76 inh 715 77 fr 585 78 yscl 455 79 shl 325 80 v dd 195 81 v ss 55 82 v 0 C112 83 v 1 C252 84 v 4 C391 85 v 5 C531 86 dio1 C671 87 com 0 C810 88 com 1 C941 89 com 2 C1071 90 dm C1865 C1201 1 dm C1579 C1357 2 com 3 C1449 3 com 4 C1320 4 com 5 C1191 5 com 6 C1062 6 com 7 C933 7 com 8 C803 8 com 9 C674 9 com 10 C545 10 com 11 C416 11 com 12 C287 12 com 13 C154 13 com 14 C28 14 com 15 101 15 com 16 230 16 com 17 359 17 com 18 489 18 com 19 618 19 com 20 747 20 com 21 876 21 com 22 1005 22 com 23 1135 23 com 24 1264 24 com 25 1393 25 com 26 1522 26 dm 1651 27 dm 1781 C1357 28 dm 1976 C1098 29 com 27 1976 C969 30 com 28 1976 C840 31 com 29 1976 C711 32 com 30 C581 33 com 31 C452 34 com 32 C323 35 com 33 C194 36 com 34 C65 37 com 35 65 38 com 36 194 39 com 37 323 40 com 38 452 41 com 39 581 42 com 40 711 43 com 41 840 44 com 42 969 45 dm 1976 1098 46 dm 1743 1357 47 dm 1614 48 com 43 1485 49 com 44 1355 50 com 45 1226 51 com 46 1097 52 com 47 968 53 com 48 839 54 com 49 709 55 com 50 580 56 com 51 451 57 com 52 322 58 com 53 193 59 com 54 63 60 com 55 C66 1357 chip size: 4.27 3.03 mm chip thickness: 400 m m (for al pad product) and 525 m m (for bump product). al pad product: pad opening is 100 100 m m. bump product: vertical au bump. bump size is 90 90 m m. bump height is 17 to 25 m m. 1 27 72 y x (0,0) 46 28 45 90 dieno. 73 pad no. 76: inh for s1d16702 * 00 ** doff for s1d16702 * 01 ** *1 *1 pad center coordinates 6. pad pad layout
s1d16702 series 5C6 epson rev.1.0 (s1d16702 * 00 ** ) doff contents of fr com output voltage shift register high high v 5 (select level) high low v 0 low high v 1 (non-select low v 4 level) low fixed to low v 0 (non-select level) inh contents of fr com output voltage shift register high high v 5 (select level) high low v 0 low high v 1 (non-select low v 4 level) low fixed to low high v 1 (non-select low v 4 level) (s1d16702 * 01 ** ) 7. functional description shift register this is a bidirectional shift register to transfer common data. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver circuit this driver outputs the lcd drive voltage. the relationship among the display blanking signal inh , contents of shift register, ac converted signal fr and common output voltage is as shown in the table below: the relationship among the display blanking signal inh , contents of shift register, ac converted signal fr and common output voltage is as shown in the table below.
s1d16702 series rev.1.0 epson 5C7 dio1 yscl shl=low 1/200 duty fr 1 frame shift register (200 lines) dio2 o0 o1 o2 q0 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 q1 q2 inh 68 lines 8. timing chart
s1d16702 series 5C8 epson rev.1.0 v dd =0v parameter symbol rating unit supply voltage (1) v ss C7.0 to +0.3 v supply voltage (2) v 5 C30.0 to +0.3 v supply voltage (3) v 0 , v 1 , v 4 v 5 C0.3 to +0.3 v input voltage v i v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v output current (1) i o 20 ma output current (2) i ocom 20 ma operating temperature topr C40 to + 85 c storing temperature tstg C65 to +150 c soldering temperature and time tsol 260 c 10sec C 9. absolute maximum ratings notes: 1. the voltage of v 0 , v1 and v 4 must always satisfy the condition of v dd 3 v 0 3 v 1 3 v 4 3 v 5 . 2. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v or more can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off. 3. all the above voltage is based on v dd = 0 v.
s1d16702 series rev.1.0 epson 5C9 condition C C functional operation recommended value recommended value recommended value v ss =C2.7v to C5.5v v ss =C2.7v to C5.5v i oh =C0.3ma i oh =C0.2ma (v ss =C2.7 to C4.5v) i ol =+0.3ma i ol =+0.2ma (v ss =C2.7 to C4.5v) v ss v in 0v v ss v in 0v v 5 =C7.0 to C28.0v v ih =v dd , v il =v ss d von v 5 = =0.5v C20.0v v ss =C5.0v, v ih =vdd, v il =v ss , f yscl =12khz, frame frequency=60hz input data; high at no load every 1/200 duy other conditions are the same as v ss = C3.0 v v ss =C5.0v, v 1 =C2.0v, v 4 =C18.0v, v 5 =C20.0v other conditions are the same as in the item of i ss1 . ta=25 c min. C5.5 C28.0 C C2.5 2/9v 5 v 5 0.2v ss v ss 0.2v ss v ss C 0.4 v ss C C C C C C C C C typ. C5.0 C C C C C C C C C C C C C C 0.70 7 5 7 C C max. C2.7 C7.0 C7.0 0 v dd 7/9v 5 0 0.8v ss 0 0.85v ss 0 v ss +0.4 2.0 5.0 25 1.40 15 10 15 8 15 unit v v v v v v v v v v v v m a m a m a k w m a m a pf pf parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage (1) low input voltage (1) high input voltage (2) low input voltage (2) high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance unless otherwise specified, v dd = v 0 = 0v, v ss = C5.0v 10%, ta = C40 to 85 c. symbol v ss v 5 v 5 v 0 v 1 v 4 v ih v il v iht v ilt v oh v ol i li i li/o i dds r com i ss1 i ss2 c i c i/o applicable pin v ss v 5 v 5 v 0 v 1 v 4 dio1, dio2, yscl, shl, fr inh dio1, dio2 yscl, shl, inh, fr dio1, dio2 v dd com0 to com99 v ss v 5 yscl, shl, inh, fr dio1, dio2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when the v 1 , v 4 , v 0 or v 5 level is output 10. electrical characteristics dc characteristics
s1d16702 series 5C10 epson rev.1.0 ?.0 ?.4 ?.0 ?.0 ?.0 ?.5 ?. v ss ( v ) ?0 ?8 ?0 ?0 ? 0 0 v 5 (v) operating voltage range operating voltage range vss C v5 v 5 voltage must be set within the following operating voltage range of v ss C v 5 .
s1d16702 series rev.1.0 epson 5C11 fr yscl t r t f t wclh t dfr v ih =0.2 v ss v il =0.8 v ss t ds t dh t ccl t wcll dio1 dio2 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 500 C ns yscl high pulsewidth t wclh C70Cns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 100 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 1000 C ns yscl high pulsewidth t wclh C 160 C ns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 200 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns the standard applicable to t ccl , t wclh , t wcll , t ds and t dh when v ss = C2.4 v must be 1.3 times of that applies when v ss = C2.7 v to C4.5 v. ac characteristics input timing characteristics
s1d16702 series 5C12 epson rev.1.0 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 30 300 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to C 3.0 m s (inh to com output) delay time tpd cinh C28.0v (fr to com output) delay time tpd cfr cl=100pf C 3.0 m s unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 60 600 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to C 3.0 m s (inh to com output) delay time tpd cinh C28.0v (fr to com output) delay time tpd cfr cl=100pf C 3.0 m s fr vn?.5v vn+0.5v t pddocl t pdccl t pdcfr t pdcinh yscl v ih =0.2 v ss v il =0.8 v ss inh com dio1 dio2 the standard applicable when v ss = C2.4 v must be 1.3 times of that applies when v ss = C2.7 v to C4.5 v. output timing characteristics
s1d16702 series rev.1.0 epson 5C13 11. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is the most simple to divide the resistance of potential as shown in the connection example. on the other hand, to obtain a high quality display, it is necessary to raise the accuracy and constancy of each voltage level and to set the divided resistance value as low as possible in the range of system power capacity. especially when a low-power lcd driving is required, set the divided resistance to a higher value and drive the lcd with a voltage follower by means of operational amplifier instead. in taking into consideration of a case where the operational amplifier is employed, the maximum potential level v 0 for lcd driving has been isolated from the v dd pin. when the potential of v 0 lowers than that of v dd and the potential difference between the two becomes larger, however, the capacity of lcd drive output driver lowers. to avoid it, use the system with the potential difference of 0 v to 2.5 v between v 0 and v dd . when no operational amplifier is used, connect v 0 and v dd pins. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating, an overcurrent flows and lsi breaks down in some cases. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off ... lcd driving system off ? logic system off or simultaneous off of the both precautions: users of this development specification are reminded of the following precautions. 1. this development specification is subject to change without previous notice. 2. this specificatino does not warrant the user to exercise the industrial property right or other rights, nor does this specification vest such rights to the user. application examples provided in this specification are solely intended to ensure better understanding of the product. the manufacturer shall not be liable for any circuit related problem arising from using such examples. numeric representation of measure or size provided in the characteristics table is one obtained from the numeric line. 3. no part of this specification may be reproduced or duplicated in any form or by any means without the written permission of the manufacturer. 4. as for use of semiconductor elements, users are required to pay attention to the following points. [precautions on the product handling in light] characteristics of semiconductor elements are changed if they are exposed to light. thus, exposing this ic to light can result in its in malfunction. in order to prevent ic malfunctioning due to light, make sure that the following measures are taken for the boards or products equipped with our ic. (1) design and mounting procedure employed do not allow light to ic. (2) the inspection process is implemented in the environment that does not allow light to ic. (3) light shielding measures are established not only for surface of ic but also for rear face and side faces, too.
s1d16702 series 5C14 epson rev.1.0 s1d16702 * 00 ** s1d16300 ***** function bidirectional shift register bidirectional shift register inh inh 68 output segments 68 output segments output tr configuration fig. 1 fig. 2 pad layout identical to the equivalent product C pad coordinates different from the equivalent product C com v 0 v 1 v 4 v 5 com v 0 v 5 v 1 v 4 fig. 2 fig. 1 12. different points from replacement product
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in pursuit of ?aving?technology , epson electronic devices. our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers?dreams. epson is energy savings. 4.5mm notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notics. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no repersesnation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ?seiko epson corporation 2001, all rights reserved.
mf425 - 05 technical manual s1d16000 series technical manual ieee1394 controller s1r76801f00a technical manual s1d16000 series epson electronic devices website electronic devices marketing division first issue november,1990 printed may,2001 in japan h a 4.5mm this manual was made with recycle paper, and printed using soy-based inks.

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